The present invention relates to a phase-locked loop for an electronic circuit and more particularly a high speed PLL clock multiplier.
A phase-locked loop (PLL) is an electronic feedback system that generates a signal, the phase of which is locked to the phase of an input or “reference” signal. This is accomplished in a common negative feedback configuration by comparing the output of a voltage controlled oscillator or divider to the input reference signal using a phase and frequency detector. The phase detector output is then used to drive the phase of the oscillator towards that of the input reference signal. Since a single integrated circuit can provide a complete phase-lock-loop building block, the technique is widely used in a variety of electronic applications. Output frequencies range from a fraction of a cycle per second up to many gigahertz.
A problem arises when the PLL must be capable of accepting an input reference signal that can vary widely. What is needed is a stable PLL circuit that can be adapt to a wide range of input reference signals.